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 MC74HC86A Quad 2-Input Exclusive OR Gate
High-Performance Silicon-Gate CMOS
The MC74HC86A is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Features http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 N SUFFIX CASE 646 1
* * * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with JEDEC Standard No. 7A Requirements Chip Complexity: 56 FETs or 14 Equivalent Gates Pb-Free Packages are Available
14 1
MC74HC86AN AWLYYWWG
14 14 1 SOIC-14 D SUFFIX CASE 751A 1 HC86AG AWLYWW
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 HC 86A ALYWG G
14 SOEIAJ-14 F SUFFIX CASE 965 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) 74HC86A ALYWG
14 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 4
1
Publication Order Number: MC74HC86A/D
MC74HC86A
PIN ASSIGNMENT
A1 B1 Y1 A2 B2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3 A1 B1 A2 B2 A3 B3 A4
LOGIC DIAGRAM
1 2 4 5 9 10 12 13 3 Y1
6
Y2
8
Y3
11
FUNCTION TABLE
Inputs A L L H H B L H L H Output Y L H H L
B4
Y4
Y= AB = AB + AB
PIN 14 = VCC PIN 7 = GND
ORDERING INFORMATION
Device MC74HC86AN MC74HC86ANG MC74HC86AD MC74HC86ADG MC74HC86ADR2 MC74HC86ADR2G MC74HC86ADTR2 MC74HC86ADTR2G MC74HC86AF MC74HC86AFG MC74HC86AFEL MC74HC86AFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 / Tape & Reel 50 Units / Rail 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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2
MC74HC86A
I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I III I I I I I IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIII I II I I I III I I I I I IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIII II III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I IIIIIIIIIIIIIIIIIIIIIII III II II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIII III III I I III I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I I
III I I I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I IIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIII III I I I I I I IIIIIIIIIIII I II I I III IIII I I I I IIIIIIIIIIIIIIIII II III I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I I IIIIIIIIIIII I II I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
VCC Vin Iin Vout Iout PD SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Output Current, per Pin Value Unit V V V - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 mA mA mA ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA Parameter Min 2.0 0 Max 6.0 VCC Unit V V DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
- 55 0 0 0
+ 125 1000 500 400
_C ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
V
|Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA
2.48 3.98 5.48 0.1 0.1 0.1
2.34 3.84 5.34 0.1 0.1 0.1
2.20 3.70 5.20 0.1 0.1 0.1
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
V
|Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA
0.26 0.26 0.26
0.33 0.33 0.33
0.40 0.40 0.40
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3
MC74HC86A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I
Guaranteed Limit v 85_C 1.0 10 Symbol Iin ICC Parameter Test Conditions VCC V 6.0 6.0 - 55 to 25_C 0.1 1.0 v 125_C 1.0 40 Unit mA mA Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND Iout = 0 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t, = tf = 6 ns)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIII III I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIII III I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I I I I IIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIII I II
Symbol tPLH, tPHL Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C 100 80 20 17 75 30 15 13 10 v 85_C 125 90 25 21 95 40 19 16 10 v 125_C 150 110 31 26 110 55 22 19 10 Unit ns Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) ns Cin Maximum Input Capacitance pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 33
2f
Guaranteed Limit
CPD
Power Dissipation Capacitance (Per Gate)*
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D). tr INPUT A OR B tPLH 90% OUTPUT Y 50% 10% tTLH tTHL 90% 50% 10% tPHL tf VCC
+ ICC VCC . For load considerations, see Chapter 2 of the
GND DEVICE UNDER TEST
TEST POINT OUTPUT CL*
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
A
Y B
Figure 3. Expanded Logic Diagram (1/4 of Device) http://onsemi.com
4
MC74HC86A
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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5
MC74HC86A
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC74HC86A
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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7
EEE CCC EEE CCC CCC
A -V-
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 -W- K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HC86A
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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8
MC74HC86A/D


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